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Magic Mailing List |
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From: John Griessen (john_g AT cibolo DOT com) Date: Sun Mar 30 2003 - 15:48:19 EST
On Sun, 2003-03-30 at 13:44, cfk wrote: > Great John: > Theres something that Tim put into the build a few weeks ago at my > suggestion that you might find interesting. If you look at wrapper.tcl at > about line 802, you'll find the commented out line 'bind $(winname) <motion> > "::magic::cursorview $(winname)"' removing the comment and recompiling with > tcl and invoking magic with magic -w will give you a real-time cursor > position in magic units from the magic origin on your drawing. Please let > the group know if you find it useful. I'll do that before I start the tutorial, thanks. > Additionally, if you compile tclspice, > you can load tclspice from the magic tkcon window with the invocation 'load > /usr/lib/libspice" (or wherever libspice was compiled to on your Debian > system). At that point, you can do an extract all, exttospice and actually > plot spice rise/fall times, transfer functions and such directly from layout > geometry. You will need to write a spice circuit that includes the extracted > circuit to include power supply, gnd, input stimulus (pwl stuff), but once > that runs, you can then just say "plot in out" (if you have an in and an out > node) and see the results without leaving magic. > > Charles Krinke The spice from layout extraction sounds very good for optimizing driver chains, and for non-clocked self-timed circuits. It also makes me think of extracting in2out delay times via a script that runs on all standard cells with the inputs and outputs loaded as in the circuit. That might take some sim time, but if it could be done background to layout efforts, and saved away as a netlist annotation property list, it would be valuable for critical timing paths. If such a list could be used by Primetime instead of nonlinear wireload models...a tighter clocked design with known timing margin could be easy. Do you have any tutorial and magic study suggestions for a EE designer of chip logic, FPGA logic, board level systems, board and chip layout? I may get some RFID tag chip work coming up....Any study suggestions for that? John Griessen
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