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Magic Mailing List |
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From: cfk (cfk AT pacbell DOT net) Date: Sun Mar 30 2003 - 16:08:55 EST
Dear John:
Well, the tutorials are a great start. I had to do each 2-3 times before
I actually began *getting* it. It is overwhelming to take a new graphics
program and try to figure out which buttons to push. By the time you get to
tut8 & tut11 you will appreciate things like routing, layout simulation,
netlisting and the like. I found that working with some standard cells that
I could appreciate gave me a great boost. You can find the cells I have been
studying at http://www.rsl.ukans.edu/~mlinhart/magic. Just download his
scmos library and his padframe library and you will be able to load them
into magic.
I am working on a networking project, and found that using the padframe
library and one or two cells (invf100 specifically) allowed me to make a few
conceptual drawings of a proposed chip with pads and even make some subcell
hierarchy and drop in a prototypical PCI interface (just I/O defined,
nothing more complicated then that). I was able to do a 'plot postscript
<file>.ps', load it with a postscript editor in Linux (I use gimp) and print
out a color plot of the floorplan of a proposed chip.
On the RFID, I would imagine you will have a combination of logic
expressable as standard cells and some custom analog circuitry for the RF
circuitry. Before just suggesting books, perhaps you could tell us which
ones you allready have in your library and perhaps we can suggest a few
interesting ones for your project.
Magic is not a pancea for everything. There is a learning curve involved
that is measured more in weeks/months then in hours/days. I also have been
doing FPGA, board level stuff for some time and it is quite interesting to
be able to visualize a chip design, it is like well *magic*.
Charles
> > Great John:
> > Theres something that Tim put into the build a few weeks ago at my
> > suggestion that you might find interesting. If you look at wrapper.tcl
at
> > about line 802, you'll find the commented out line 'bind $(winname)
<motion>
> > "::magic::cursorview $(winname)"' removing the comment and recompiling
with
> > tcl and invoking magic with magic -w will give you a real-time cursor
> > position in magic units from the magic origin on your drawing. Please
let
> > the group know if you find it useful.
> I'll do that before I start the tutorial, thanks.
>
> > Additionally, if you compile tclspice,
> > you can load tclspice from the magic tkcon window with the invocation
'load
> > /usr/lib/libspice" (or wherever libspice was compiled to on your Debian
> > system). At that point, you can do an extract all, exttospice and
actually
> > plot spice rise/fall times, transfer functions and such directly from
layout
> > geometry. You will need to write a spice circuit that includes the
extracted
> > circuit to include power supply, gnd, input stimulus (pwl stuff), but
once
> > that runs, you can then just say "plot in out" (if you have an in and an
out
> > node) and see the results without leaving magic.
> >
> > Charles Krinke
>
> The spice from layout extraction sounds very good for optimizing driver
> chains, and for non-clocked self-timed circuits. It also makes me think
> of extracting in2out delay times via a script that runs on all standard
> cells with the inputs and outputs loaded as in the circuit. That might
> take some sim time, but if it could be done background to layout
> efforts, and saved away as a netlist annotation property list, it would
> be valuable for critical timing paths. If such a list could be used by
> Primetime instead of nonlinear wireload models...a tighter clocked
> design with known timing margin could be easy.
>
> Do you have any tutorial and magic study suggestions for a EE designer
> of chip logic, FPGA logic, board level systems, board and chip layout?
>
> I may get some RFID tag chip work coming up....Any study suggestions for
> that?
>
> John Griessen
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