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Hello everyone,
   Does anybody know whether there exists an "extractor torture test"
which can be used to pit a device extraction model against all sorts
of bizarre transistor geometries (annular, waffle, bends, kinks,
etc.) with transistors that have been characterized for an effective
length and width (or set of lengths and widths) based on empirical
data gathered from the fabricated device?
   Barring that, can anyone point me to published papers on what
they believe to be the "best" (in any sense) model for handling
extraction of corners and other unusual geometry in a transistor
gate.
   I have just implemented an extension in magic which finds and
extracts an effective length and width for annular (ring) devices,
and correctly extracted several different device layouts.  At least,
it extracts width as the midline around the active part of the
transistor.  The standard magic extractor bombs on annular devices,
because its only concept of length is measured where it sees poly
crossing active.  In annular devices, this only happens on the
"tab", so the transistor length it calculates is the width of the
tab, not the length of the transistor (unless they happen to be the
same).
					Regards,
					Tim

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