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From: R. Timothy Edwards (tim AT stravinsky DOT jhuapl.edu)
Date: Mon Apr 21 2003 - 12:33:31 EDT

  • Next message: R. Timothy Edwards: "RE: electrical connectivity between nodes"

    Dear Charles,
    
       Sheesh, I go to the beach for the weekend and the email just piles
    up.  Plus, the beach was COLD.  Anyway. . .
    
       I looked into the problem a bit and decided that something I did while
    implementing the new extraction methods has fouled up the code for the
    old extraction method, which was *supposed* to have maintained perfect
    backward compatibility but obviously didn't.
    
       I will track down the error and post a fix for it.
    
       However, some small explanation should be given regarding the new
    extraction methods, which are intended to (eventually) replace the old
    ones.  These are giving me the correct answers for width and length,
    by the way, which is why I assume the L/W errors can be traced back to
    something I failed to do to keep the original code exactly as it was.
    The new methods replace the "fet" lines in the tech file.  The keyword
    "fet" is replaced by the keyword "device", with the following
    variations:
    
    	device mosfet <name> <gate_types> <source,drain_types> \
    			<substrate_types>|None \
    			<default_substrate_name> \
    			[perim_cap] [area_cap]
    	device bjt <name> <base_types> <emitter_types> <collector_types>
    	device resistor <name> <resistor_types> <terminal_types>
    	device capacitor <name> <top_types> <bottom_types> [<perim_cap>] \
    			<area_cap>
    	device subcircuit <name> <gate_types> [<terminal_types> \
    			[<substrate_types>]]
    
       The "capacitor" and "resistor" entries will write "C" and "R" records,
    respectively, to the SPICE deck, avoiding the post-processing usually
    associated with capacitor and resistor extraction in magic.
    
    					Regards,
    					Tim
    


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