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From: Atif Nadeem (anadeemk AT yahoo DOT com)
Date: Tue May 20 2003 - 09:05:19 EDT

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    I have successfully installed and used some open source tools for the complete VLSI Design flow (Please comment out on my design flow) on RedHat Linux. Here i go
 
1. Veriwell: Verilog simulator for HDL description of my circuit
2.Xcircuit: For Schematic Design of my circuit
3. IRSIM: For simulation of Schematic design circuit
4. Magic: For Layout of my circuit
5.IRSIM: For layout simulation
6. Gemini/Netgen: For LVS layout vs Schematic
 
Step2-6 are quite interrelated where output of one step is the input to other step but step1 seems to be totally separate from other steps. Can you please guide me what is the relationship between this step1 with all other steps?  How can I interrelate it with other steps so that output of this step1 will be the input to any other step from 2-6?
 
7. Xilinx: For VLSI implementation using FPGA
if I use FPGA, can you please tell me what will be the design flow in that case? 
 
Regards
Atif



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