Architecture

My group investigates the case when no clocks are used in the entire design. The results of this work can be used as-is, or in conjunction with partially clocked designs (GALS, LAGS) that contain asynchronous components. We are currently investigating energy and performance characteristics of components in asynchronous architectures.

We are also investigating the impact of 3D integration on system architecture. This raises some new issues that involve thermal management, interconnect scaling, and system organization.

A more detailed description as to why we consider this an interesting approach is provided in the paper A Case for Asynchronous Computer Architecture listed below.

Collaborators

Prof. José Martínez

Prof. Emin Gün Sirer

Prof. Sandip Tiwari

Students

David Biermann (Ph.D. 2006)

David Fang

Publications

Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks, June 2007. (abstract, pdf)

Filipp Akopyan, Rajit Manohar, and Alyssa Apsel. A level-crossing Flash Asynchronous Analog-to-Digital Converter. Proceedings of the 12th International Symposium on Asynchronous Circuits and Systems, March 2006. (abstract, pdf)

David Fang, Filipp Akopyan, and Rajit Manohar. Self-Timed Thermally Aware Circuits. IEEE Computer Society Annual Symposium on VLSI, March 2006. (abstract, pdf)

Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, and Sandip Tiwari. Mapping Multimedia Applications to 3-D System-on-Chip . Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, May 2005.

Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. BitSNAP: Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, March 2005. (abstract, pdf, ps)

Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. An Ultra-low-power Processor for Sensor Networks. Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, October 2004. (abstract, pdf, ps)

David Biermann, Emin Gün Sirer, and Rajit Manohar. A Rate Matching-based Approach to Dynamic Voltage Scaling. Proceedings of the First Watson Conference on the Interaction between Architecture, Circuits, and Compilers, October 2004. (abstract, pdf, ps)

David Fang and Rajit Manohar. Non-Uniform Access Asynchronous Register Files. Proceedings of the 10th International Symposium on Asynchronous Circuits and Systems, April 2004.

John Teifel and Rajit Manohar. A High Speed Clockless Serial Link Tranceiver. Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems, pp. 151--161, Vancouver, BC, May 2003. (abstract, pdf, ps)

Virantha Ekanayake and Rajit Manohar. Asynchronous DRAM Design and Synthesis. Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems, pp. 174--183, Vancouver, BC, May 2003. (abstract, pdf, ps)

John Teifel, David Fang, David Biermann, Clinton Kelly IV, and Rajit Manohar. Energy-Efficient Pipelines. Proceedings of the 8th International Symposium on Asynchronous Circuits and Systems, pp. 21--31, Manchester, UK, March 2002. (abstract, ps)

Rajit Manohar. Width-Adaptive Data Word Architectures. Proceedings of the 19th Conference on Advanced Research in VLSI, pp. 112--129, Salt Lake City, Utah, March 2001. (abstract, ps)

Rajit Manohar, Mika Nyström, and Alain J. Martin. Precise Exceptions in Asynchronous Processors. Proceedings of the 19th Conference on Advanced Research in VLSI, pp. 16--28, Salt Lake City, Utah, March 2001. (abstract, ps)

Rajit Manohar. A Case for Asynchronous Computer Architecture. Proceedings of the ISCA Workshop on Complexity-Effective Design, June 2000. (abstract, ps)

Rajit Manohar and Mark Heinrich. A Case For Asynchronous Active Memories. ISCA 2000 Solving the Memory Wall Problem Workshop, June 2000. (abstract, ps)