Asynchronous VLSI and Architecture Cornell University About | Chips | People | Teaching | Research | Papers | Sponsors | News The group is moving to Yale in January 2017. Publications organized by research area are listed with pages describing the area. Note that publications are provided here only to ensure timely dissemination of technical work on a non-commercial basis. Copyright are maintained by the authors or by other copyright holders. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright. [Papers]  [Theses]  [Reports] Refereed Papers: Neuromorphic Computing Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John Arthur, Paul Merolla, N Imam, Yutaka Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael Beakes, Bernard Brezzo, Jente Kuang, Rajit Manohar, William Risk, Bryan Jackson, and Dharmendra Modha. TrueNorth: Design and Tool Flow of a 65mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(10), October 2015. (abstract, pdf)   — Keynote paper Giovanni Rovere, Nabil Imam, Rajit Manohar, and Chiara Bartolozzi. A QDI Asynchronous AER Serializer/Deserializer Link in 180nm for Event-Based Sensors for Robotic Applications. Proceedings of the International Symposium on Circuits and Systems, May 2015. (abstract) Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul A. Merolla, Pallab Datta, Marc Gonzalez Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steve Millman, Nabil Imam, Emmett McQuinn, Yutaka T. Nakamura, Ivan Vo, Chen Guo, Don Nguyen, Scott Lekuch, Sameh Assad, Daniel Friedman, Bryan L. Jackson, Myron D. Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha. Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100x Speedup in Time-to-Solution and ~100,000x Reduction in Energy-to-Solution. Proceedings of Supercomputing 2014, November 2014. (abstract, pdf)   — ACM Gordon Bell Prize finalist Paul A. Merolla, John V. Arthur, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Jun Sawada, Filipp Akopyan, Bryan L. Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, Bernad Brezzo, Ivan Vo, Steven K. Esser, Rathinakumar Appuswamy, Brian Taba, Arnon Amir, Myron D. Flickner, William P. Risk, Rajit Manohar, and Dharmendra Modha. A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface. Science, 345(6197):668--673, August 2014. (abstract, pdf)   — IBM Research 2014 Pat Goldberg Math/CS/EE Best Paper Award Saber Moradi, Nabil Imam, Rajit Manohar, and Giacomo Indiveri. A Memory-Efficient Routing Method for Large-Scale Spiking Neural Networks. 21st European Conference on Circuit Theory and Design, September 2013. (abstract, pdf) Nabil Imam, Kyle Wecker, Jonathan Tse, Robert Karmazin, and Rajit Manohar. Neural Spiking Dynamics in Asynchronous Digital Circuits. 2013 International Joint Conference on Neural Networks (IJCNN), August 2013. (abstract, pdf) Rajit Manohar. Scalable Routing in Large-Scale Neuromorphic Systems. Symposium on Large-Scale Neuromorphic Systems at the Annual International Conference of the IEEE Engineering in Medicine and Biology Society [invited], August 2012. John Arthur, Paul Merolla, Filipp Akopyan, Rodrigo Alvarez, Andrew Cassidy, Shyamal Chandra, Steven Esser, Nabil Imam, William Risk, Daniel Rubin, Rajit Manohar and Dharmendra Modha. Building Block of a Programmable Neuromorphic Substrate: A Digital Neurosynaptic Core. 2012 International Joint Conference on Neural Networks (IJCNN), June 2012. (abstract, pdf) Nabil Imam, Thomas Cleland, Rajit Manohar, Paul Merolla, John Arthur, Filipp Akopyan, and Dharmendra Modha. Implementation of Olfactory Bulb Glomerular Layer Computation in a Digital Neurosynaptic Core. Frontiers of Neuromorphic Engineering, Vol. 6, Number 83, June 2012. (abstract, pdf) Nabil Imam, Filipp Akopyan, Paul Merolla, John Arthur, Rajit Manohar, and Dharmendra Modha. A Digital Neurosynaptic Core Using Event-Driven QDI Circuits. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf)   — Best paper award Paul Merolla, John Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra Modha. A Digital Neurosynaptic Core Using Embedded Crossbar Memory with 45pJ per Spike in 45nm. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2011. (abstract, pdf) Nabil Imam and Rajit Manohar. Address-Event Communication Using Token-Ring Mutual Exclusion. Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2011. (abstract, pdf) Jon Russo, Mohammed Amduka, Keith Pendersen, Richard Lethin, Jonathan Springer, Rajit Manohar, Rami Melhem. Enabling Cognitive Architectures for UAV Mission Planning. Proceedings of the High Performance Embedded Computing Workshop (HPEC), September 2006. (abstract, pdf)   — Best paper award Rajit Manohar and K. Mani Chandy. Δ-Dataflow Networks for Event Stream Processing. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, November 2004. (abstract, pdf, ps)   — Best paper award Design Methodology and Automation Filipp Akopyan, Carlos Tadeo Ortega Otero, and Rajit Manohar. Hybrid Synchronous-Asynchronous Tool Flow for Emerging VLSI Design. IEEE International Workshop on Logic Synthesis, June 2016. Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Concurrent Systems. Work-in-progress session, Design Automation Conference, June 2016. Sandra Jackson and Rajit Manohar. Gradual Synchronization. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2016. (abstract)   — Best paper finalist Stephen Longfield, Brittany Nkounkou, Rajit Manohar, and Ross Tate. Preventing Glitches and Short Circuits in High-Level Self-Timed Chip Specifications. 36th Annual ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), June 2015. (abstract, pdf) Rajit Manohar and Yoram Moses. Analyzing Isochronic Forks with Potential Causality. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf)   — Best paper finalist Robert Karmazin, Stephen Longfield, Carlos Tadeo Ortega Otero, and Rajit Manohar. Timing Driven Placement for Quasi Delay-Insensitive Circuits. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf) Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015. Stephen Longfield and Rajit Manohar. Removing Concurrency for Rapid Functional Verification. Proceedings of the 2014 International Conference on Computer-Aided Design (ICCAD), November 2014. (abstract, pdf) Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf) Robert Karmazin, Carlos Otero, and Rajit Manohar. CellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf) Stephen Longfield and Rajit Manohar. Inverting Martin Synthesis for Verification. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf)   — Best paper award Song Peng, David Fang, John Teifel, and Rajit Manohar. Automated Synthesis for Asynchronous FPGAs. 13th ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 2005. (abstract, pdf, ps) John Teifel and Rajit Manohar. Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps) Rajit Manohar. Scalable Formal Design Methods for Asynchronous VLSI. Proceedings of the 29th ACM SIGPLAN/SIGACT Conference on the Principles of Programming Languages [invited] (POPL), Portland, OR, January 2002. Rajit Manohar. An Analysis of Reshuffled Handshaking Expansions. Proceedings of the 7th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 96--105, Salt Lake City, Utah, March 2001. (abstract, ps) Rajit Manohar. The Entropy of Traces in Parallel Computation. IEEE Transactions on Information Theory, 45(5):1606--1608, July 1999. (abstract, pdf, ps) Rajit Manohar, Tak-Kwan Lee, and Alain J. Martin. Projection: A Synthesis Technique for Concurrent Systems. Proceedings of the 5th IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pp. 125--134, April 1999. (abstract, pdf, ps) K. Rustan M. Leino and Rajit Manohar. Joining Specification Statements. Theoretical Computer Science, 216:375-394, March 1999. (abstract, ps) Rajit Manohar and Alain J. Martin. Slack Elasticity in Concurent Computing . Proceedings of the Fourth International Conference on the Mathematics of Program Construction (MPC), Lecture Notes in Computer Science 1422, pp. 272-285, Springer-Verlag 1998. (abstract, pdf, ps) Energy-efficient VLSI and Arithmetic Rajit Manohar. Comparing Stochastic and Deterministic Computing. IEEE Computer Architecture Letters, 14(2):119--122, July 2015. (abstract, pdf)   — Best of Computer Architecture Letters Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf) Benjamin Tang, Stephen Longfield, Rajit Manohar, and Sunil Bhave. Low Power ASIC GPS Tracking Loops: Quantifying the Trade-Offs Between Area, Power and Accuracy. Proc. ION GNSS Technical Meeting, September 2012.    — Best presentation award Basit Riaz Sheikh and Rajit Manohar. An Asynchronous Floating-Point Multiplier. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf) Basit Riaz Sheikh and Rajit Manohar. Energy-efficient Pipeline Templates for High Performance Asynchronous Circuits. ACM Journal on Emerging Technologies in Computer Systems (special issue on asynchrony in system design), 7(4), December 2011. (abstract, pdf) Basit Riaz Sheikh and Rajit Manohar. An Operand-Optimized Asynchronous IEEE 754 Double-precision floating-point adder. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf)   — Best paper award Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. Static Power Reduction Techniques for Asynchronous Circuits. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf) Christopher LaFrieda and Rajit Manohar. Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits. Proceedings of the 15th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2009. (abstract, pdf) David Fang, Filipp Akopyan, and Rajit Manohar. Self-Timed Thermally Aware Circuits. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), March 2006. (abstract, pdf) David Fang and Rajit Manohar. Non-Uniform Access Asynchronous Register Files. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps) John Teifel and Rajit Manohar. A High Speed Clockless Serial Link Tranceiver. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 151--161, Vancouver, BC, May 2003. (abstract, pdf, ps) Virantha Ekanayake and Rajit Manohar. Asynchronous DRAM Design and Synthesis. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 174--183, Vancouver, BC, May 2003. (abstract, pdf, ps) John Teifel, David Fang, David Biermann, Clinton Kelly IV, and Rajit Manohar. Energy-Efficient Pipelines. Proceedings of the 8th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 21--31, Manchester, UK, March 2002. (abstract, ps) Rajit Manohar. Width-Adaptive Data Word Architectures. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 112--129, Salt Lake City, Utah, March 2001. (abstract, pdf, ps) Rajit Manohar. The Entropy of Traces in Parallel Computation. IEEE Transactions on Information Theory, 45(5):1606--1608, July 1999. (abstract, pdf, ps) Rajit Manohar and José A. Tierno. Asynchronous Parallel Prefix Computation. IEEE Transactions on Computers, Vol. 47, No. 11, 1244-1252, November 1998. (abstract, ps) Asynchronous FPGAs Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015. Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf) Christopher LaFrieda, Benjamin Hill, and Rajit Manohar. An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf)   — Best paper finalist S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf) Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007. Rajit Manohar. Reconfigurable Asynchronous Logic. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2006. (abstract, pdf) David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf) Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006. David Fang, John Teifel, and Rajit Manohar. A High-Performance Asynchronous FPGA: Test Results. 2005 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005. (abstract, pdf) Song Peng, David Fang, John Teifel, and Rajit Manohar. Automated Synthesis for Asynchronous FPGAs. 13th ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 2005. (abstract, pdf, ps) John Teifel and Rajit Manohar. An Asynchronous Dataflow FPGA Architecture. IEEE Transactions on Computers (special issue on field-programmable logic), November 2004. (abstract, pdf) John Teifel and Rajit Manohar. Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps) John Teifel and Rajit Manohar. Highly Pipelined Asynchronous FPGAs. 12th ACM International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, February 2004. [Please see abstract]. (abstract, pdf, ps) John Teifel and Rajit Manohar. Programmable Asynchronous Pipeline Arrays. Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), pp. 345--354, Lisbon, Portugal, September 2003. (abstract, pdf, ps) Ultra Low Power Embedded Systems Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. AES Hardware-Software Co-Design in WSN. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf) Benjamin Tang, Sunil Bhave, and Rajit Manohar. Low Power Asynchronous VLSI with NEM Relays. Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2014. (abstract, pdf)   — Best paper finalist Jaeyeon Kihm, François Guimbretière, Julia Karl, Rajit Manohar. Using Asymmetric Cores to Reduce Power Consumption for Interactive Devices with Bi-Stable Displays. Proceedings of the ACM CHI Conference on Human Factors in Computing Systems (CHI), April 2014. (abstract, pdf) Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar. ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes. Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2014. (abstract, pdf) François Guimbretière, Shenwei Liu, Han Wang, Rajit Manohar. An Asymmetric Dual-Processor Architecture for Low Power Information Appliances. ACM Transactions on Embedded Computing Systems, 13(4), February 2014. (abstract, pdf) Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf) Benjamin Tang, Stephen Longfield, Rajit Manohar, and Sunil Bhave. Low Power ASIC GPS Tracking Loops: Quantifying the Trade-Offs Between Area, Power and Accuracy. Proc. ION GNSS Technical Meeting, September 2012.    — Best presentation award Benjamin Tang, Stephen Longfield, Sunil Bhave, and Rajit Manohar. A Low Power Asynchronous GPS Baseband Processor. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf) Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. Static Power Reduction Techniques for Asynchronous Circuits. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf) Filipp Akopyan, Rajit Manohar, and A. Apsel. A level-crossing Flash Asynchronous Analog-to-Digital Converter. Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2006. (abstract, pdf)   — Best paper award Yao-Win Hong, Birsen Sirkeci-Mergen, Anna Scaglione, and Rajit Manohar. Dense Sensor Networks are also Energy-efficient: when `more' is `less'. Proceedings of MILCOM 2005, October 2005. (abstract, pdf)   — IEEE Fred Ellersick Award for the best unclassified paper at MILCOM Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. BitSNAP: Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2005. (abstract, pdf, ps)   — Best paper finalist Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. An Ultra-low-power Processor for Sensor Networks. Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004. (abstract, pdf, ps) Clinton Kelly IV, Virantha Ekanayake, and Rajit Manohar. SNAP: A Sensor Network Asynchronous Processor. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 24--33, Vancouver, BC, May 2003. (abstract, pdf, ps) Rajit Manohar and Anna Scaglione. Power Optimal Routing in Wireless Networks. IEEE International Conference on Communications, pp. 2979--2984, Anchorage, AK, May 2003. (abstract, pdf) Asynchronous Computer Architecture Sandra Jackson and Rajit Manohar. Gradual Synchronization. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2016. (abstract)   — Best paper finalist Rajit Manohar. Comparing Stochastic and Deterministic Computing. IEEE Computer Architecture Letters, 14(2):119--122, July 2015. (abstract, pdf)   — Best of Computer Architecture Letters Paul A. Merolla, John V. Arthur, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Jun Sawada, Filipp Akopyan, Bryan L. Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, Bernad Brezzo, Ivan Vo, Steven K. Esser, Rathinakumar Appuswamy, Brian Taba, Arnon Amir, Myron D. Flickner, William P. Risk, Rajit Manohar, and Dharmendra Modha. A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface. Science, 345(6197):668--673, August 2014. (abstract, pdf)   — IBM Research 2014 Pat Goldberg Math/CS/EE Best Paper Award Jaeyeon Kihm, François Guimbretière, Julia Karl, Rajit Manohar. Using Asymmetric Cores to Reduce Power Consumption for Interactive Devices with Bi-Stable Displays. Proceedings of the ACM CHI Conference on Human Factors in Computing Systems (CHI), April 2014. (abstract, pdf) Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar. ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes. Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2014. (abstract, pdf) François Guimbretière, Shenwei Liu, Han Wang, Rajit Manohar. An Asymmetric Dual-Processor Architecture for Low Power Information Appliances. ACM Transactions on Embedded Computing Systems, 13(4), February 2014. (abstract, pdf) Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf) Jon Russo, Mohammed Amduka, Keith Pendersen, Richard Lethin, Jonathan Springer, Rajit Manohar, Rami Melhem. Enabling Cognitive Architectures for UAV Mission Planning. Proceedings of the High Performance Embedded Computing Workshop (HPEC), September 2006. (abstract, pdf)   — Best paper award Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. BitSNAP: Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2005. (abstract, pdf, ps)   — Best paper finalist Rajit Manohar and K. Mani Chandy. Δ-Dataflow Networks for Event Stream Processing. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, November 2004. (abstract, pdf, ps)   — Best paper award Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. An Ultra-low-power Processor for Sensor Networks. Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004. (abstract, pdf, ps) David Biermann, Emin Gun Sirer, and Rajit Manohar. A Rate Matching-based Approach to Dynamic Voltage Scaling. Proceedings of the First Watson Conference on the Interaction between Architecture, Circuits, and Compilers, October 2004. (abstract, pdf, ps) David Fang and Rajit Manohar. Non-Uniform Access Asynchronous Register Files. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps) Clinton Kelly IV and Rajit Manohar. An Event-Synchronization Protocol for Parallel Simulation of Large-Scale Wireless Networks. Seventh IEEE International Symposium on Distributed Simulation and Real Time Applications, October 2003. (abstract, pdf, ps) Clinton Kelly IV, Virantha Ekanayake, and Rajit Manohar. SNAP: A Sensor Network Asynchronous Processor. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 24--33, Vancouver, BC, May 2003. (abstract, pdf, ps) Virantha Ekanayake and Rajit Manohar. Asynchronous DRAM Design and Synthesis. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 174--183, Vancouver, BC, May 2003. (abstract, pdf, ps) Rajit Manohar and Clinton Kelly IV. Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI. IEEE Communications Magazine, pp. 149--155, November 2001. (abstract, pdf, ps) Rajit Manohar. Width-Adaptive Data Word Architectures. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 112--129, Salt Lake City, Utah, March 2001. (abstract, pdf, ps) Rajit Manohar, Mika Nyström, and Alain J. Martin. Precise Exceptions in Asynchronous Processors. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 16--28, Salt Lake City, Utah, March 2001. (abstract, pdf, ps) Rajit Manohar. A Case for Asynchronous Computer Architecture. Proceedings of the ISCA Workshop on Complexity-Effective Design, June 2000. (abstract, pdf, ps) Rajit Manohar and Mark Heinrich. A Case For Asynchronous Active Memories. ISCA 2000 Solving the Memory Wall Problem Workshop, June 2000. (abstract, ps) Three Dimensional Integration Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf) T. Robert Harris, Shivam Priyadarshi, Samson Melamed, Carlos Otero, Rajit Manohar, Steven R. Dooley, Nikhil M. Kriplani, W. Rhett Davis, Paul D. Franzon, and Michael B. Steer. A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits. IEEE Transactions on Components and Packaging Technologies, 2(4):660–667, April 2012. (abstract) S. Priyadarshi, T. R. Harris, S. Melamed, C. Otero, N. Kriplani, C. E. Christoffersen, R. Manohar, S. R. Dooley, W. R. Davis, P. D. Franzon, and M. B. Steer. Dynamic electrothermal simulation of three dimensional integrated circuits using standard cell macromodels. IET Circuits, Devices, and Systems, 6(1):35–44, January 2012. Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra Jackson, and Rajit Manohar. Variability in 3-D Integrated Circuits. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2008. (abstract, pdf) David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf) Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf) Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, and Sandip Tiwari. Mapping Multimedia Applications to 3-D System-on-Chip. Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, May 2005. Resilient Asynchronous Systems S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf) Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf) Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007. Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006. Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf) Song Peng and Rajit Manohar. Self-healing Asynchronous Arrays. Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2006. (abstract, pdf) Song Peng and Rajit Manohar. Efficient Failure Detection in Pipelined Asynchronous Circuits. Proceedings of the IEEE Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), October 2005. (abstract, pdf) Song Peng and Rajit Manohar. Fault Tolerant Asynchronous Adders through Dynamic Self-reconfiguration. Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2005. (abstract, pdf) Christopher LaFrieda and Rajit Manohar. Robust Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits. Proceedings of the International Conference on Dependable Systems and Networks (DSN), July 2004. (abstract, pdf, ps) Theses: Ph.D. Benjamin Hill. Architecture and Synthesis for Dynamically Reconfigurable Asynchronous FPGAs. Ph.D. thesis, December 2015. Robert Karmazin. Automating the Physical Design of Asynchronous Circuits. Ph.D. thesis, November 2015. Jonathan Tse. A Study of Asynchronous Links and Logic. Ph.D. thesis, October 2015. Stephen Longfield. Constructive Verification of Quasi Delay-Insensitive Circuits. Ph.D. thesis, March 2015. Carlos Tadeo Ortega Otero. Asynchronous Design for Ubiquitous Computing. Ph.D. thesis, July 2014. Sandra Jackson. Gradual Synchronization. Ph.D. thesis, July 2014. Nabil Imam. Canonical Neural Computations in Asynchronous Neuromorphic Circuits. Ph.D. thesis, April 2014. Benjamin Zhong Xian Tang. Exploiting Asynchrony in GPS Receiver Systems to Enable Ultra-Low-Power Operation. Ph.D. thesis, January 2014. Basit Riaz Sheikh. Operand-Optimized Asynchronous Floating-Point Arithmetic. Ph.D. thesis, August 2011. Filipp Akopyan. Hybrid Synchronous/Asynchronous Design. Ph.D. thesis, April 2011. Christopher LaFrieda. Relaxed Quasi Delay-Insensitive Circuits. Ph.D. thesis, December 2009. David Fang. A Profiling Infrastructure for Performance Evaluation of Asynchronous Systems. Ph.D. thesis, May 2008. David Biermann. A Workload Adaptive Voltage Scaling Multiple Clock Domain Architecture. Ph.D. thesis, September 2006. Song Peng. Implementing Self-Healing Behavior in Quasi Delay-Insensitive Circuits. Ph.D. thesis, August 2006. Clinton Kelly, IV. The Design and Implementation of an Asynchronous Network on a Chip. Ph.D. thesis, July 2005. Virantha Ekanayake. Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Ph.D. thesis, May 2005. John Teifel. Fast Prototyping of Asynchronous Logic. Ph.D. thesis, August 2004. M.S. Yuan Tian. A Parallel Implementation of Hierarchical Belief Propagation. M.S. thesis, May 2013. Stephen Longfield. Design and Implementation of a Low Power Asynchronous GPS Baseband Processor. M.S. thesis, March 2013. Carlos Tadeo Ortega Otero. Static Power Reduction Techniques for Asynchronous Circuits. M.S. thesis, May 2012. Nabil Imam. A Communication Infrastructure for Multi-Chip Neuromorphic Systems. M.S. thesis, May 2012. Christopher LaFrieda. Custom-Quality Wire Routing Using Modern Design Rules. M.S. thesis, August 2005. Filipp Akopyan. Asynchronous Analog-to-Digital Converter for Low Power Applications. M.S. thesis, August 2005. David Fang. Width-Adaptive and Non-Uniform Access Asynchronous Register Files. M.S. thesis, January, 2004. Clinton Kelly, IV. Wireless Network Simulation Done Faster than Real Time. M.S. thesis, January, 2003. Virantha Ekanayake. Asynchronous Dynamic Random Access Memories. M.S. thesis, January, 2003. David Biermann. Multiprocessor-Enabled Asynchronous Cache Controller. M.S. thesis, January 2003. John Teifel. Interchip Communication in Asynchronous VLSI Systems. M.S. thesis, May 2002. Other Technical Reports: Rajit Manohar and Alain J. Martin. Pipelined Mutual Exclusion and the Design of an Asynchronous Microprocessor. Cornell Computer Systems Lab Technical Report CSL-TR-2001-1017, November 2001. Rajit Manohar and Mika Nyström. Implications of Voltage Scaling in Asynchronous Architectures. Cornell Computer Systems Lab Technical Report CSL-TR-2001-1013, April 2001. Rajit Manohar and Mark Heinrich. The Branch Processor Architecture. Cornell Computer Systems Lab Technical Report CSL-TR-1999-1000, November 1999. Rajit Manohar. Variable-Precision Number Representations for Asynchronous VLSI. Cornell Computer Systems Lab Technical Report CSL-TR-1999-999, September 1999. Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12. webmaster@vlsi.cornell.edu Ithaca . Directions to CSL