Publications

The documents listed below are included by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright.

Selected Papers (full list)

John Teifel and Rajit Manohar. Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. Proceedings of the 10th International Symposium on Asynchronous Circuits and Systems, April 2004. (abstract, pdf, ps)
This paper describes an intermediate representation--static token form--that is suitable for dataflow-style synthesis of high-level asynchronous specifications. Both normal and loop-carried dependencies are handled in a unified framework.

John Teifel and Rajit Manohar. Programmable Asynchronous Pipeline Arrays. Proceedings of the 13th International Conference on Field Programmable Logic and Applications, Lisbon, Portugal, September 2003. (abstract, ps, pdf)
This paper describes an asynchronous FPGA architecture that is programmable at the pipeline stage level. We report performance numbers that, for the first time, are competitive with (and actually better than) clocked FPGA architectures, and that are also competitive with full custom asynchronous design.

Clinton Kelly IV, Virantha Ekanayake, and Rajit Manohar. SNAP: A Sensor Network Asynchronous Processor. Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems, Vancouver, BC, May 2003. (abstract, ps, pdf)
This paper presents the first microprocessor optimized for sensor network applications and wireless network simulation. The entire processor is clockless and event-driven, allowing for very fast transitions to/from its idle state as well as energy-efficient operation. The processor can handle 10 sensor events/sec with 20-40 nW of active power.

John Teifel, David Fang, David Biermann, Clinton Kelly, IV, and Rajit Manohar. Energy-Efficient Pipelines. Proceedings of the Eighth International Symposium on Asynchronous Circuits and Systems, Manchester, UK, March 2002. (abstract, ps)
This paper presents an analysis of asynchronous pipelines that are optimized for both energy and delay. The optimization criteria are of form Et^a, where a is a parameter that picks the tradeoff between energy and delay.

Rajit Manohar and Clinton Kelly, IV. Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI. IEEE Communications Magazine, November 2001. (abstract, ps, pdf)
This paper presents the connection between asynchronous VLSI and networks, and argues that efficient hardware network emulators can be built using asynchronous design techniques.

Rajit Manohar. Width-Adaptive Data Word Architectures. Proceedings of the 19th Conference on Advanced Research in VLSI, Salt Lake City, Utah, March 2001. (abstract, ps)
This paper presents a comprehensive set of techniques for designing adaptive processors that only have datapath switching activity for the significant digits in a binary number. Independently, Jim Smith's group at Wisconsin provided an architectural evaluation of clocked datapaths that use similar concepts but a different representation (MICRO, December 2000).

Rajit Manohar, Tak-Kwan Lee, and Alain J. Martin. Projection: A Synthesis Technique for Concurrent Systems. Proceedings of the Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 1999. (abstract, ps)
This paper presents a powerful program transformation that can be used to reason about the correctness of asynchronous pipelines. In particular, asynchronous computations pipelined according to their dataflow graph can be shown to be correct in a trivial manner.

Rajit Manohar and José A. Tierno. Asynchronous Parallel Prefix Computation. IEEE Transactions on Computers, 47(11):1244--1252, November 1998. (abstract, ps)
This paper presents the design of an N-input asynchronous parallel prefix circuit that has an expected latency that is O(log log N) when the prefix operator has a right zero. In particular, this circuit can be used to construct an asynchronous adder that has O(log log N) expected latency. Asymptotically, our design has the best attainable: (i) throughput; (ii) worst-case latency; (iii) average-case latency. Given its performance characteristics, it also has the best possible area.

Rajit Manohar and Alain J. Martin. Slack Elasticity in Concurrent Computing. Proceedings of the Fourth International Conference on the Mathematics of Program Construction, Lecture Notes in Computer Science 1422, pp. 272-285, Springer-Verlag 1998. (abstract, ps)
This paper presents an analysis of the effect of increasing the synchronization slack between two communication actions on the correctness of the computation. In particular, it is shown that a large class of asynchronous computations remain unchanged when the slack is increased. This has important consequences for asynchronous microprocessor design, and shows that most local re-pipelining decisions do not affect global correctness.

Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul Penzes, Robert Southworth, Uri V. Cummings, and Tak-Kwan Lee. The Design of an Asynchronous MIPS R3000 microprocessor. Proceedings of the 17th Conference on Advanced Research in VLSI, pp. 164--181, September 1997. (abstract, ps, pdf)
This paper was the first published asynchronous microprocessor that that was competitive with (actually better than) clocked microprocessors in terms of performance. This paper introduced a number of important techniques at the circuit and microarchitecture level that were used to achieve high performance without resorting to aggressive timing assumptions.

José A. Tierno, Rajit Manohar, and Alain J. Martin. The Energy and Entropy of VLSI Computations. Proceedings of the Second International Symposium on Advanced Research in Asynchronous Circuits and Systems. March 1996. (abstract, ps)
This paper presents the connection between energy, entropy, and asynchronous computation. This is a follow-on to an earlier paper on low energy asynchronous memories that contains some of the theory presented here.

Rajit Manohar and Alain J. Martin. Quasi-delay-insensitive circuits are Turing-complete. Invited article, Second International Symposium on Advanced Research in Asynchronous Circuits and Systems. March 1996. Available as Caltech technical report CS-TR-95-11, November 1995. (abstract, ps)
This paper presents the connection between hazard-free quasi-delay insensitive (QDI) circuits, the stability property of gates, and the confluence property of computations. It also shows that the synthesis method used for QDI circuits is complete.



Errata: The paper on "Slack Elasticity" published in the proceedings of the conference on the Mathematics of Program Construction (1998) has an error in the final printed version due to an unfortunate oversight in proof-reading. Corollary 1 should read: If a system satisfies its specification when the slack on channel c is k, and if it is unchanged when the slack on channel c is l (> k), it satisfies its specification when the slack on c is s, for all s satisfying k <= s <= l. An examination of the proof shows that this is the statement being established, so the proof is identical. This statement was the version presented at the conference as well.